Output

ABSTRACT

AN ELASPED TIME DIGITAL COMMUNICATION SYSTEM IS DISCLOSED WHEREIN BOTH THE DIGITAL INFORMATION CONTENT AND THE TIMING OR CLOCK INFORMATION IS REPRESENTED BY THE ELAPSED TIME FOR TWO SUCCESSIVE TRANSITIONS BETWEEN ELECTRICAL STATES. AFTER A FIRST OR INITIATING TRANSITION TO AN ACTIVE STATE, EACH SUCCESSIVE TRANSITION INDICATES THAT INFORMATION IS AVAILABLE. BY MEASURING THE TIME BETWEEN SUCCESSIVE TRANSITIONS, BOTH INFORMATION CONTENT AND TIMING SIGNALS ARE RECOVERED.

Nov. 20, 1973 w B BUEHRLE Re. 27,810

TWO-STATE UOMMUNIUATIUN DIIVIUILIS HAVING COMBINED CIII CK ANI)INFORMATION SIGNALS Original Filed Sept 2, 196b 2 ShPetn-fihmat I 40 \L-I 22 44 K k PULSE TRANSMITTER GENERATOR 38 CLOCK PULSES 1 I I ANO INPUTI 52 SHIFT I 42 REGISTER 0 OR I 32 50 T OUTPUT FINAL DIGIT TRANSMIT R FF0 A F. F j QR S N I 0 S I I 34 M 24 30 I PROGRAM R 0 48 COUNTER I II L26 K-3 46 F INFORMATION 2 SIGNAL SOURCE ENCODE wAvEFORMS DIGIT POSITIONI I I 2 3 4 INFORMATION O I I IOA OUTPUT FF l8 CLOCKPULSESIII I III IIII IIIII 26A wORO PULSES 4 I I EOM. PULSES I I I 46A LOAD SIR. I l 34ATRANSMIT FF J W SENSE FF. W

INVENTOR.

William B. Buehr/e ATTYS.

NOV. 20, 1973 w BUEI-IRLE Re. 27,810

TWO-STATE COMMUNIATION DEVICES HAVING COMBINED CLOCK AND INFORMATIONSIGNALS Original Filed Sept. 12, 1966 2 Sheets-Sheet T 56\ 64 CLOCKPULSES Q PULSE GEN, 1 o S D REcEIvER 6O 58 OR c I SO T 54 I FF DELAYED ROR C PULSE GEN (H 6) I A (Fig.5) 68 I I IOU 98 ilil ENABLE S s I 70INCOMING MC T '02 u."

MESSAGE I M EE FF E I C Fig.3 IR C (FIg.6I 5

I E EQM C T M E R (Figs) TIME FIRST WORD LAST WORD 04 DIGIT POSITION '45I 2 3 4 5 6 7 8 9 IO EOM B RECEIVED WAVE CLOCK PULSES I P P96] I I l I II I /62A "0" TIMER I I I I I l I l I l I /74A "I" TIMER F/94I I I I 1/76A "EoM" TIMER /78A "o FF. W/BOA "I" F.F. W

"o" OUTPUT I I I I i "I" OUTPUT I I I l I I I I I I I I I I I DECODEDINFOR. o l I 0 0 I o I o I EOM ENABLE F I94 72 INVENTOR. William B.Buehr/e ATTY's.

United States Patent Oflice Reissued Nov. 20, 1973 TWO-STAGECOMMUNICATION DEVICES HAV- ING COMBINED CLOCK AND INFORMATION SIGNALSWilliam B. Buehrle, Phoenix, Ariz., assignor to Motorola,

Inc., Franklin Park, Ill.

Original No. 3,510,780, dated May 5, 1970, Ser. No. 584,035, Sept. 12,1966. Application for reissue July 21, 1971, Ser. No. 164,791

Int. Cl. H04b 1/16 US. Cl. 325-321 6 Claims Matter enclosed in heavybrackets II] appears in the original patent but forms no part of thisreissue specification; matter printed in italics indicates the additionsmade by reissue.

ABSTRACT OF THE DISCLOSURE This invention relates generally to digitalinformation communication devices and systems and particularly to thosedevices and systems wherein a change in electrical states indicates bothtiming and information to be translated.

In providing digital signals over a communication channel, especially achannel having substantial noise, it is desirable to provide frequentclock or timing signals to ensure synchronization of the receiver andthe trans mitter. In most systems there is a compromise between theinformation rate, pass band of the channel, and the furnishing ofclocking signals. Generally, the higher the information rate, thegreater the requirement is for absolute synchronization between thetransmitter and receiver at opposite ends of an information channel. Ina channel having high information rates, the drift between theoscillators or other timing mechanisms may be limited to a 0.5% beforeinformation is lost or erroneously introduced into the system. Insystems employing lower rates of information transfer, the timingtolerances are correspondingly increased.

Prior art communication systems have used coding and signal indicatingtechniques wherein the direction of the signal or its magnitude is usedto indicate information content. For example, in Teletype or teleprintersystems, the mark-space signals are used to convey information and alsoin some respect provide timing. Such systems are referred to asreturn-to-zero (RTZ). Such communication systems require that betweensuccessive signals indicating information items that the signal returnto a zero or reference condition. The space between two successivesignals indicating information is therefore unused. Improvements overRTZ are the so-called non-return-tozero (NRZ) and thenon-return-to-zero-change-on-one (NRZl) schemes. The NRZ and NRZlprovide an improvement in that there is no return to a referencecondition between successive information indicating signals. In thelatter systems, wherein the information content of successive signals ordigit positions is unchanged, there is no clocking information provided;i.e., there are no changes in electrical states. Some magnetic tapesystems, using the NRZI code, require phase modulation schemes toprovide clocking information. Such devices require complicated andextensive equipments which are not justified in all communicationapplications. Other communications systems have a three-state signalwhich consists of a neutral state bounded by two bi-polar conditions forindicating information. Here again, the signal amplitude and polarityindicates information with the three states requiring a wider pass bandthan that is required for a two state communications system. Also, morecostly equipment is required. Yet, other communications systems anddevices have resorted to adaptive and self-clocking systems forovercoming noise interference in information channels. Such systems arequite expensive even though they do provide one solution for theclocking and information rate problem.

Therefore, it is an object of this invention to provide a simple,inexpensive and reliable two-state communication device and system whichis relatively insensitive to the noise.

It is another object of this invention to provide communication deviceswhich utilize a combined clocking and information signal.

It is a further object of this invention to provide communicationdevices and systems having independent operating timing elements withthe system design permitting a large variation in timing elements fromstation to station and yet provide reliable communications.

A communication system using this invention has the feature that alltransitions between two signal states except the first and last occuringtransitions indicate both timing and availability of information. Alsoeach bit of information requires such a transition.

Referring now to the accompanying drawing, wherein:

FIG. 1 is a block-flow diagram illustrating an encoder which may be usedto provide wave forms according to the teachings of this invention.

FIG. 2 is a set of idealized wave forms with indicated informationrepresentations used to explain the operation of the FIG. 1 encoder.

FIG. 3 is a block flow diagram of a receiver-decoder usable with thesubject invention.

FIG. 4 is a set of idealized wave forms used to explain the operation ofthe FIG. 3 decoder.

FIG. 5 is a schematic diagram of a delayed pulse generator usable withthe FIG. 3 decoder.

FIG. 6 is a schematic diagram of a unijunction type of timing unitusable with the FIG. 3 illustrated decoder.

According to this invention, information to be transmitted through aninformation channel is represented by elapsed time between twosuccessive transitions between electrical states in the system, forexample mark and space potentials in a telegraph or teleprinter system.The successive transitions provide timing or clock information as wellas indicating that information is indicatable. After a first orinitiating transition between a reference state to an active state, eachsuccesive transition indicates that information is available. The timebetween successive transitions are then measured. For example, in abinary system, a first elapsed time, for example, one millisecond, mayrepresent a binary zero. A second and greater period of elapsed time,for example one and onehalf milliseconds, may represent a binary one.The end of the message is indicatable by an elapsed time equal to twomilliseconds, for example. All the transitions intermediate the initialtransition and the transition immediately following an elapsed time oftwo milliseconds indicate information and also provide synchronization.

The above described wave may be generated by selectively toggling atwo-state counter, such as a flip flop, on a variable time basis toprovide successive transitions between mark and space potentials orelectric states. Such a wave is detected or decoded by sensing suchtransitions and utilizing timing devices for measuring the time betweensuccessive transitions, and indicating such elapsed time as areproduction of such binary information. The transitions are also usedas clock pulses in the receiver. The end of message (EOM) twomillisecond elapsed time is used to automatically deactivate thereceiver. By using the above method, as many digits or bits of binaryinformation may be transmitted in one message as one pleases. With eachbit of information, also including clocking information, the length ofthe message will never adversely affect operating reliability. Forconvenience, the message may be broken into units of five bits withsuccessive units of five bits being transmitted as a unitary message.

Paying particular attention now to FIGS. 1 and 2, an encoding system isdescribed for generating communication waves according to the teachingsof this invention. Referring firstly to FIG. 2, wave form A has anelapsed time of one unit of time, such as one millisecond, betweensuccessive transitions 14 and 16 to represent binary zero.Correspondingly, an elapsed time of one and one-half millisecondsbetween successive transitions 16 and 18 represents a binary 1. Theportion 12 appearing before first transition 14 contains no transitionsindicating that no information is being transferred over the informationchannel (not shown). In the illustrated wave form, space-to-marktransition 14 is a first occurring transition and all succeedingtransitions, such as 16 and 18, provide both clocking signals andindicate that information is available; i.e., a binary zero or a binaryone. For convenience in the embodiment to be described, each message isdivided into words. There are five digits of information in each word.Referring to FIG. 2, the first row indicates the digit positions 1through 10, constituting the two words being transmitted. This shortmessage illustrates how two words are merged into a single succession oftransitions to form a unitary message and how the beginning and end of amessage is indicated. In a practical case 70-75 bits could be includedin a message.

The FIG. 1 encoder includes periodic pulse generator 20 providing aseries of clock pulses 20A (FIG. 2). These clock pulses provide thebasic timing of the encoding and decoding system. The periodic pulsegenerator is of the type that has a voltage control connected to line 22and for altering the periodicity of the generated pulses. In thisparticular instance, there are provided two period durations oroperating states, one having a basic unit of time representing a binaryzero (which is one millisecond) and a second period of time which isused to represent a binary one (which is one and one-half milliseconds).Generator 20 supplies its clock pulses continuously to program counter24. Counter 24 is operative in response to the clock pulses to programthe operation of the encoder for transmitting a plurality of bits ofinformation received in five bit word format. In the particularembodiment counter 24 emits a pulse over line 26 each time it hascounted five pulses from generator 20 (one for each bit of information).The emitted pulse indicates that a word of five bits of information maybe transmitted and may indicate that a unit of five bits has beentransmitted. Such pulses 26A are called word pulses." Information signalsource 28 receives a word pulse and is responsive thereto when it hasinformation to be transmitted to provide a set of five signals over thefive parallel lines 30 to input shift register 32. The signaltransmission over the lines 30 is such that a signal indicationaccording to wave form 34A is always provided through OR circuit 34 toset transmit flip flop 36 to its active condition. This action indicatesthere are information signals in register 32 for transmission. Flip flop36 opens certain control gates as will be described to effect the wavegeneration and resultant transmission.

In one embodiment of the transferring of information signals to register32, a three-state signal was used wherein there was a center neutralvoltage with binary ones and zeros being indicated respectively bysignals having plus and minus voltages with respect to said "neutraPvoltage. Therefore, OR circuit 34 would always pass either a plus orminus signal to set flip flop 36. Alternatively, lines 30 may operate ina two-state mode with an M or N code providing M binary one signals froman N bit word through OR circuit 34 for setting transmit flip flop 36.Further, if a straight binary code is used, a control line (not shown)may be connected between information source 28 and the set input of flipflop 36 for setting that flip flop each time information is transferredto input shift register 32. For example, pure binary information asillustrated in FIG. 2 may be used. Such binary information may actuallybe NRZI encoded information wherein a binary zero indicates no change instate; i.e., no information change, while a binary one indicates achange in state, therefore indicating that the binary informationrepresented is being changed. Other binary codes may be used such asbinary coded decimal, excess three, etc., the selection of such codingis not important to practicing the present invention.

Transmit flip flop 36 initiates the operation by supplying wave 26A ofFIG. 2 to open AND gate 38 for passing clock pulses appearing on line 40supplied by generator 20. Each time AND gate 38 passes such a clockpulse, output flip flop 42 is switched to its other state irrespectiveof the present state, (hereinafter referred to as toggling) forproviding the output flip flop wave form 10A. Transmitter 44 sends wave10A to an information channel (not shown). As will become apparent, flipflop 42 is initially cleared or reset to its zero indicating state asrepresented by portion 12 of wave form 10A.

The generation of the first spaee-to-mark transition 14 will now bedescribed. Clock pulses from generator 20 continuously shift the signalcontents of shift register (SR)32. Shift register 32 has five digitpositions plus a sensing digit position 33 which supplies a frequencycontrol voltage over line 22 to generator 20. Initially, the shiftregister 32 is loaded by the load SR-pulse 34A after a word pulse 26A.The next occurring clock pulse is one millisecond later and issimultaneously passed by AND gate 38 to toggle flip flop 42 creatingtransition 14 and shifts the signal contents of register 32 one digitposition to the right inserting the binary zero contained in digitposition one (FIG. 2) into sense flip flop 33. Since it is a zero, theclock pulse generator 20 still operates on a one millisecond period.Also, the clock pulse advances program counter 24 one count.

The second transition 16 (mark-to-space) is initiated by the clock pulseoccurring at the end of digit position one. AND circuit 38 passes thesecond occurring clock pulse to toggle flip flop 42 back to its clearedor reset state, generating transition 16. Simultaneously therewith,counter 24 has increased its count to two (binary 010) and shiftregister 32 is shifted right one digit position inserting the binary onerepresenting signal of digit position two in sensing flip flop 33.Immediately, the voltage over line 22 is altered to increase the periodof generator 20 to one and one half milliseconds. Therefore, transition18 occurs one and one-half milliseconds later than transition 16.

The third transition 18 (space-to-mark) is generated as aforedescribedwith the clock pulses also shifting register 32 to insert the thirddigit position contained binary one signal into flip flop 33 and advancecounter 24 to a count of three. Upon reaching the count of three, apulse is emitted by counter 24 over line 46 which is used as will belater described to indicate end-of-message (EOM). AND gate 48 is closedby transmit flip flop 36 being in a set state and therefore blocks theemitted pulse one line 46. Flip flop 33 has received the binary 1 infrom the third digit position, therefore the elapsed time until the nexttransition following transition 18 is also one and one-halfmilliseconds. The fourth transition, immediately following digitposition three, is generated as the aforedescribed with the counter 24now having a count of four and a binary zero signal being shifted intoflip flop 33 for decreasing the period of generator 20.

The fifth occuring transition may indicate the end of a message.However, it is desired to transmit digits 6-10, therefore the EOM signalmust be blocked. Counter 24 has been advanced to a count of fiveemitting a pulse over line 26 indicating to information signal source 28that information signals may again be inserted into shift reglater 32.It may be noted that line 26 world pulse 26A resets transmit flip flop36 disabling or closing AND gate 38 inhibiting transmission of clockpulses from line 40 to toggle output flip flop 42. To complete themessage, another transition at the end of digit position 5 must beprovided for. However, in this particular illustration, informationsignal source 28 provides a second set of five information pulses orsignals to shift register 32 to set flip flop 36 before the occurrenceof the next succeeding clock pulse. Such resetting and subsequentsetting of flip flop 36 is indicated by the negative going portion ofwave 36A in digit portion 5 of FIG. 2. Flip flop 36 having been setbefore the clock pulse occurring at the end of the digit position five,the transitions of the sixth, seventh and eighth digit positions aresupplied as aforedescribed for earlier occurring transistors.

The procedure for indicating end-of-message (EOM) is initiated at theend of digit position nine (digit position 4 in the second word) by wordpulse 26A. Transmit flip flop 36 is reset to its inactive conditionclosing AND gate 38 preventing clock pulses from line 40 from togglingoutput flip flop 42. Word pulse 26A is also sent to information signalsource 28 which in this case does not respond permitting EOM to begenerated. Since AND circuit 38 is closed, provisions are made to supplythe last transition appearing at the termination of digit position 10.To this end, final-digit transmit flip flop 50 and OR gate 52 areprovided. As soon as transmit flip flop 36 has been set, its set outputsignal is supplied to the set input of flip flop 50, setting it to anactive condition. Flip flop 50 provides an output signal to OR circuit52 which is combined with the set output signal from flip flop 36 toopen AND gate 38. Flip flop 50 has the output signal of AND gate 38connected to its reset input. Therefore, each time flip flop 42 istoggled, flip flop 50 receives an impulse on its reset input. However,transmit flip flop 36 is continuously driving the flip flop 50 set inputkeeping it set. Because of the inherent delays through the counter 24,word pulse 26A does not reset transmit flip flop 36 until after AND gate38 has passed its clock pulse from line 40. Flip flop 50 is reset by ANDgate 38 output pulse just prior to the time transmit flip flop 36 isreset. Therefore, flip flop 50 is still receiving the set signal fromflip flop 36, keeping flip flop 50 in the set condition until the nextappearing clock pulse. Such action is indicated by dotted line 50A inFIG. 2. 0n the last transition at the end of digit period 10, ANDcircuit 38 is enabled or opened by final digit transmit flip flop 50 andis automatically reset by the pulse output of AND circuit 38.

The end of message (EOM) indication is completed in two milliseconds byprogram counter 24 emitting a second pulse over line 46. In FIG. 2, EOMpulse 48A is passed by AND circuit 48, now opened by transmit flip flop36 in its reset state, which clears flip Hop 42 two clock pulse periodsafter the final transition of digit period 10. Sense flip flop 33 isreset causing generator 20 to operate on a one millisecond period. Itwill be remembered that word pulse 26A (first occurring pulse in EOM)occurred at the end of digit period nine and that three clock pulseperiods (counter 24 advanced by three) thereafter, the pulse is emittedover line 46. Since digit period or position takes up one of the threedigit periods, the end of message indication is provided by an elapsedtime of two clock pulse or digit periods between the transition at theend of digit period 10 and the transition caused by pulse 48A.

Referring now to FIGS. 3 and 4 and an exemplary decoding operationutilizing the teachings of this invention is described. In FIG. 4,received wave 10B is identical to the output wave 10A of FIG. 2, as justdescribed. Wave 10B is received by two-state receiver 54, which may beany known form of communication receiver. Wave 10B is then supplied todelayed-pulse generators 56 and 58 for detecting the transitions.Delayed pulse generator 56 detects and indicates the mark-to-spacetransitions. It will be remembered that the no-message condition ofwaves 10A and 10B are at the space potential, as indicated by numeral 12in FIG. 2. The delayed pulse generator construction is shown in FIG. 5and will be later described. To make both the generators 56 and 58identical, inverting amplifiers 60 is inserted in the input portion ofthe generator 58 to invert the direction of transition, the purpose ofwhich will be come apparent. Generators 56 and 58 combine their outputpulses in OR circuit 62 to provide a series of clock pulses 62A overline 64 .for timing the operation of the decoding system. By comparingclock pulses 62A with clock pulses 20A of FIG. 2, it may be noted thatafter the first transition of waves 10A and 10B, the spacing between theclock pulses in the decoder is identical to that in the encoder.

The detection of the first transition in a word of wave 10B is alwaysdetected by generator 58 because the first transition is always aspace-to-mark transition. Generator 58 supplies a pulse over line 68,indicative of such transition, setting incoming-message flip flop 70.Flip flop 70 supplies its set condition indication as an enablingvoltage over line 72 for activating the three timers 74, 76 and 78 whichare used respectively for timing the elapsed time between successivetransitions for detecting a binary zero, binary one, and EOM. Theconstruction of such timers is illustrated in schematic form in FIG. 6and will be later fully described. The characteristics of the threetimers are identical in that after being reset by a clock pulseappearing on line 64, each of the timers will emit a pulse after apredetermined elapsed time. For example, timer 74 will emit a pulseafter one millisecond, indicating a binary zero; timer 76 emits a pulseafter one and one-half milliseconds, indicating a binary one; and EOMtimer 78 emits a pulse two milliseconds after being reset, indicatingend-of-message. Each time a clock pulse appears on line 64, all threetimers are simultaneously reset. Detection of a binary zero as indicatedby an elapsed time of one millisecond will be first described. Forpurposes of discussion, the first binary zero appearing in digitposition will be utilized. The first clock pulse in wave 62A isgenerated from the first transition 14B (wave 108). The clock pulseappears at a time subsequent to transition 14B. Generators 56 and 58 areconstructed not to emit a pulse until a certain energy level has beenreceived. Such an energy threshold eliminates random noise in thechannel from introducing false information into the system. The firstappearing clock pulse also resets timer 74 causing it to begin itstiming operation. After a time just short of one millisecond, a pulse 81in a string of pulses 74A is emitted to set zero indicating flip flop80. Zero flip flop supplies an output pulse 80A to AND circuit 86, thesetting operation being indicated by the rising wave front 84 in wave80A. Immediately subsequent to timer 74 emitted pulse 81, secondoccurring clock pulse 82 is emitted by generator 56 as caused by thesecond appearing transition at the end of digit period number one. Suchclock pulse is provided over line 64 and through AND circuit 86, openedby flip flop 80 to indicate a zero binary digit indicating signal hasbeen received. It should also be noted that the second clock pulse 82resets timers 76 and 78 to restart the timing operation without theirhaving emitted any pulses.

Detection of a binary one indicating elapsed time will now be described.For purposes of: illustration, the second digit position, having abinary one, will be discussed. It will be remembered that flip flop 80has been set. Whenever timer 76 emits a pulse indicating a binary one,it is supplied to OR circuit 90 to reset flip flop 80 for closing ANDcircuit 86. In the second digit position, zero timer 74 emits pulse 92of series of pulses 74A setting flip flop 80. Subsequent thereto, "one"timer 76 emits pulse 94 resetting flip flop 80 and simultaneouslysetting flip flop 98 just prior to the initiation of clock pulse 96 ofclock pulses 62A as emitted by generator 58. Clock pulse 96 is suppliedto AND circuits 86 and 100 and is passed through AND circuit 100 asopened by flip flop 98 to indicate a received binary one signal. Flipflop 98 is reset by the signals through OR circuit 102 as received fromtimers 74 and 78. Therefore, the two flip flops, 80 and 98, arerespectively reset each time either timers 74 or 76 indicate informationmay be received other than that indicated by such flip flops. Subsequentdigit positions are detected as aforedescribed. In transition from thefirst to the succeeding words, the decoder does not see any dilferenceand operates as described.

Detection of the end-of-message (EOM) will now be described. Subsequentto the receipt of the transition at the end of digit period 10, timers74 and 76 emit several pulses as indicated in FIG. 4. These areineffective because no clock pulses 62A are generated during thisinterim period. Just prior to the final transition 104 of wave 108, EOMtimer 78 emits pulse 78A resetting flip flops 80 and 98 for preventingany spurious information indication. EOM timer 78 pulse 78A is alsosupplied to reset incoming message flip flop 70 disabling all threetimers 74, 76 and 78. Simultaneously therewith there is provided overline 105, a decode signal to apparatus (not shown) utilizing thereceived information. Such a device may be a digital computer. When thelast appearing clock pulse 62A, as caused by transition 104, appears online 64, both AND gates 86 and 100 are close and the timers 74, 76 and78 have been disabled. The decoder is now ready to receive additionalmessages.

Referring now to FIG. 5, there is shown a schematic diagram of circuitrywhich may be used to implement the delayed-pulse generators 56 and 58 ofFIG. 3. Generator 56 responds to space-to-mark transition whilegenerator 58 responds to mark-to-space. Received wave 10B is supplied tothe generator on terminal 106 for selectively turning transistor switch108 on and off according to the polarity of the received wave.Initially, all the voltage points in the circuit were --V volts becausetransistor 108 is non-conductive. When transistor 108 is conductive, RCcircuit 110 is charged positively by current flow from ground. After apredetermined time, the voltage across RC circuit 110 is sufficient toswitch unijunction transistor 112 to current conduction. Upon beingswitched on, unijunction transistor 112 provides a voltage surge whichis coupled through coupling capacitor 114 as an impulse (a clock pulse)to OR circuit 62. Therefore, the FIG. 5 circuit emits a pulse each timetransistor 108 is turned on, that is each time the received wave B goesnegative. In this regard, inverting amplifier 60 inverts the receivedwave such that the first transition 143 (which goes positive) isinverted to be a negative going transition for actuating generator 58only in response to positive going transitions. RC circuit 110 is anintegrator for detecting the amount of energy received after atransition. Such an integrator requires a strong signal to actuateunijunction transistor 112 to eliminate noise spikes commonly found incommunications channels. Resistor of RC network 110 is low value suchthat unijunction transistor 112 becomes conductive and does notoscillate. It remains conductive until transistor 108 is turned off.

Referring now to FIG. 6, there is shown in schematic form, a timer whichmay be used to implement timers 74, 76 and 78. The enable signal fromflip flop 70 (FIG. 3) is supplied over line 72 through resistor 116 tocharge capacitor 118. As capacitor 118 is charged positively withrespect to ground reference potential, unijunction transistor 120 isactuated after a delay determined by the RC time constant of capacitor118 and resistor 116 into repeated current conductions for providingcurrent surges through resistor 122. The current surge is translatedinto a voltage pulse by coupling capacitor 124 and is provided to theelements described with respect to the respective timers of FIG. 3. Byadjusting the time constant of resistor 116 and capacitor 118, differenttime delays are provided in the decoder timers. Clock pulses 62A assupplied over line 64 reset the timers by actuating transistors switch126 to current conduction. When conductive, transistor 126 presentspractically zero impedance to capacitor 118 for discharging it veryrapidly to reset the timing circuit.

What is claimed is:

1. A digital signal decoder, including in combination:

input means for receiving a signal wave characterized by a succession oftransitions between first and second states, the elapsed time betweensuccessive transitions varying between first and second intervals basedupon digital information content,

enabling means connected to said input means for providing an enablingsignal upon the receipt of the first transition of the digital signal,

first timing means coupled to said input means for initiating a firsttiming operation and generating a signal indicative of a first period ofelapsed time between successive transitions,

second timing means coupled to said input means for initiating a secondtiming operation and generate a signal indicative of a second period ofelapsed time between successive transitions, said first and secondtiming means being coupled to said enabling means whereby the first[receiving] received transition enables said timing means, and

output means connected to receive the output signals of said first andsecond timing circuits and generate a binary information signal inaccordance with the timing means signals.

2. The combination of claim 1 further comprising, third timing meanscoupled to said input means for initiating a third timing operation inresponse to the receipt of successive transitions having a prescribedelapsed time period, said third timing means providing an output signalindicating the end of the digital signal.

3. A digital signal decoder including in combination:

input means for receiving a signal wove characterized by a succession oftransitions between first and second states, the elapsed time betweensuccessive transitions varying between first and second intervals basedupon digital information content,-

timing means connected to said input means and responsive to the signalwave for producing a first output signal indicative of a first intervalof elapsed time between successive transitions and for producing asecond output signal indicative of a second in terval of elapsed timebetween successive transitions; and

output means connected to said input means and to said liming means toreceive the first and second output signals therefrom and responsive tothe signal wave and such output signal for generating a binaryinformation signal in accordance therewith.

4. The combination according to claim 3 further including means coupledwith said input means and responsive to each transition in the receivedsignal wave for resetting said timing means upon the occurrence of eachreceived transition.

5. T he combination according to claim 4 wherein said output meansincludes first and second gating means enabled, respectively, by thefirst and second output signals of said timing means, with said firstand second gating means also being coupled with said input means, saidfirst gating means providing an output signal in response to atransition in the received signal wave whenever said first gating meansis enabled by the first output signal from said timing means, saidsecond gating means pro- 9 viding an output signal in response to atransition in the received signal wave whenever said second gating meansis enabled by the second output signal from said timing means.

6. A binary digital transmission system including in combination:

means providing binary information data bits having at least one outputwith a signal having a first level appearing thereon for binar data bitsof one binary condition and a signal having a second level uppearingthereon for binary data bits of another condition; interval timing meanscoupled with the output of said means providing data bits and responsiveto the signals appearing thereon for producing output pulses at firstand second time intervals in response to the first and second signallevels respectively, appearing on the output of the source of data bits;circuit means coupled with said timing means and responsive to theoutput pulses for providing a binary output signal characterized by asuccession of transitions between first and second states, eachtransition occurring each time an output pulse is obtained from thetiming means, the elapsed time between successive transitions varyingbetween said first and second time intervals;

ALBERT J. MAYER, Primary Examiner further timing means coupled toreceive the binary output signal from said circuit means for producing afirst output signal indicative of a first interval of elapsed timebetween successive transitions and for producing a second output signalindicative of a second interval of elapsed time between successivetransitions; and

output means connected to receive the first and second output signalsfrom said further timing means for generating a binary informationsignal in accordance with the output signals from said further timingmeans.

15 of record in the patented file of this patent or the original patent.

UNITED STATES PATENTS 3,319,013 5/1967 Hodder 179-1002 3,319,013 5/1967Hadder 179-100.2

US. Cl. X.R.

